1. Field of the Invention
The invention relates to a signal processing method for temperature compensation, more particularly to a voltage-averaged temperature compensation method at start-up and corresponding circuit thereof, to produce an output voltage signal.
2. Description of the Related Art
Many devices, for example, MOS devices, have an initialization time (enable time) after receiving a supply voltage. During initialization (startup), the output states are not defined and the outputs will toggle due to temperature effects such as ambient temperature. In order to achieve a well-defined output state, a temperature compensation structure is required.
FIG. 1 is a block diagram of a typical temperature compensation structure for a reference voltage generation circuit. FIG. 2 is a diagram of an internal circuit with respect to the structure of FIG. 1. FIG. 3 is a graph of an output waveform of FIG. 2.
As shown in FIGS. 1 and 2, a resistor Rn connected in parallel to one or more diodes D (FIG. 2) can produce negative temperature current NTC (with respect to the second current generation circuit 12 of FIG. 1) through the resistor Rn and positive temperature current PTC (with respect to the first current generation circuit 11 of FIG. 1) through the one or more diodes. The resistor Rn can be a thermister with a negative temperature coefficient variation. The currents NTC and PTC are added to the drain of a PMOS device (with respect to the current addition circuit 13 of FIG. 1). For example, in this case, the drain of the PMOS device MA adds currents NTCA, PTCB of a grounded resistor RA and a grounded diode DA to a terminal TA, wherein the resistor RA and the diode DA are connected in parallel. The terminal TA is further connected to the negative terminal of an amplifier 22. The drain of the PMOS device MB adds currents NTCB, PTCB of a grounded resistor RB and a cascade of grounded resistor RN and diodes DB to a terminal TB, wherein the resistor RB and the cascade are connected in parallel. The terminal TB is further connected to the positive terminal of the amplifier 22. The drain of the PMOS device MC connected to a load resistor R adds all branch currents as a current output PTC+NTC of the entire circuit. The current output PTC+NTC is converted by the load resistor R (with respect to the current-to-voltage conversion circuit 14 of FIG. 1) and finally output in a voltage form VBG. Gates of the cited PMOS devices MA, MB, MC are connected to outputs of a start-up circuit 21 and the amplifier 22. As such, when the start-up circuit 21 sends a trigger signal SIG to turn on all PMOS devices MA, MB, MC through the cascade gates, temperature compensation is performed by the resistor RA, RB. After the temperature compensation, the compensated temperature current on terminal TB and the compensated temperature current on terminal TA are fed into positive and negative terminals of the amplifier 22 to accordingly produce an output current out. The output current out activates a desired bias current to produce a step-down voltage VBG on resistor R and the step-down voltage VBG is output to , for example, the reference voltage generation circuit of a detector as a reference voltage.
However, due to the internal impedance of the cited resistors, the VBG waveform is similar to a RLC circuits""s output response with critical damping, as shown in FIG. 3. This waveform lacks an obvious control signal with logic H/L and may cause an error control since it may be applied as a reference voltage output of a detector. Therefore, this is not suitable for the temperature compensation circuit of a reference voltage generation circuit.
Accordingly, an object of the invention is to provide a voltage-averaged temperature compensation method at start-up and corresponding circuit, to minimize the damping distortion and assure a desired output.
The invention provides a voltage-averaged temperature compensation method at start-up, comprising the steps of: implementing a first plurality of PMOS devices with gates connected to an output of a start-up circuit, sources connected to an operating voltage, and drains including a first drain, a second drain and a third drain; implementing a second plurality of PMOS devices with gates connected to an output of an amplifier, sources connected to the operating voltage, and drains connected to the drains of the first plurality of PMOS devices one-to-one; implementing a positive voltage generation device consisting of a cascade of, between the ground and the first drain, a resistor and multiple parallel diodes, wherein the connection terminal of the resistor and the one drain connects to a positive terminal of the amplifier; implementing a negative voltage generation device consisting of a grounded forward-biased diode with an anode connected to a negative terminal of the amplifier, the second drain and a voltage average circuit; implementing a load resistor between the ground and the third drain, wherein the connection terminal of the load resistor and the third drain is connected to the voltage average circuit; activating the first plurality of PMOS devices through the output of the start-up circuit to produce a damping waveform in lower region of an output voltage; and activating the second plurality of PMOS devices through the output of the amplifier, such that the voltage average circuit averages outputs of the second drain and the third drain to produce a desired waveform as a reference or control signal in upper region of the output voltage.